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One constant of CPU manufacturing for decades has been that different components on the aforementioned die must share a common process node. It's certainly possible to build a packet that combines, say, a 14nm CPU with a large pool of on-scrap enshroud congenital at 22nm, or to have a CPU built at one process node that has a GPU built at a different process node adjacent to information technology, but on the aforementioned physical slice of silicon. Intel has used both approaches in the past. At Hot Chips last week, however, the fleck manufacturer showed off something dissimilar — a new packaging solution that offers an alternative to expensive two.5D interposers (used past both AMD and Nvidia for various high-end GPUs). Intel has discussed its embedded multi-die interconnect bridge (EMIB) earlier, but it revealed boosted details at Hot Fries this year.

Here'south how Intel describes EMIB on its site: "We sought a solution that is practical to pattern, reliable across whatsoever die, and unproblematic to implement in a design. The result is the Embedded Multi-die Interconnect Bridge, affectionately abbreviated to EMIB. There can be many embedded bridges in a single substrate, providing extremely loftier I/O and well controlled electric interconnect paths between multiple dice, equally needed. Considering the chips do not take to be continued to the packet through a silicon interposer with TSVs, in that location is nothing to potentially degrade their performance. We use micro-bumps for loftier density signals, and coarser pitch, standard flip bit bumps for direct power and basis connections from chip to package."

emib-die-zoom-blue-16x9-graphic

There are theoretical advantages to using EMIB as opposed to a silicon interposer. In order to function finer, the silicon interposer has to be the combined size of all the dies to be connected. Aligning this layer and manufacturing it with the requisite number of through-silicon vias (TSVs) has historically been hard — the interposer itself is a simple sheet of silicon, but wiring the interposer up properly and connecting it to all the requisite devices is hard. The diagram below shows a ii.5D interpose at the meridian and Intel's EMIB solution at the bottom:

emib-flex-scaling-trans-16x9-graphic

Intel'due south goal is to move from a traditional monolithic CPU pattern to an approach that would allow it to mesh dissimilar components congenital on different nodes on the same physical chip. Certain components, like modems, don't require or necessarily benefit from smaller procedure shrinks. In other cases, Intel could see benefits from reserving 10nm for the hardware most likely to benefit from using it, while other components might make the transition to a new node over time. One reason Santa Clara wants to build in this stepwise fashion is that it makes it easier to deploy critical components that will benefit from new nodes first, with other hardware adopting the technology when it makes sense to practise and then.

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Images from Intel'southward Manufacturing Day earlier this year. Click to overstate.

EMIB could also bypass some of the limitations of interposers, allowing for larger chip sizes without the reticle limits that prevent interposers from growing above a certain size. Interposer designs as well require that all fleck-to-chip communication utilise the interposer layer, while EMIB allows for more than flexibility. Intel is initially deploying the technology in its FPGAs, but is conspicuously evaluating its use in other, upcoming products. Interposers and HBM2 have, thus far, been stuck at the elevation end of the GPU marketplace with express utility to other types of products. If Intel'south EMIB delivers the power consumption improvements and other benefits it promises, nosotros could run into this tech move over to Cadre in the not-too-distant future.

Now read: What is silicon, and why are computer chips fabricated from it?

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